Field of the Invention
The invention relates to an integrated memory having a plurality of memory cell arrays, which each have word lines for selecting memory cells and bit lines for reading or writing data signals of the memory cells. The invention also relates to a method for operating the integrated memory.
An integrated memory generally has one or more memory cell arrays each including bit lines and word lines. In this case, the memory cells are provided at crossover points between the bit lines and the word lines. The memory cells are in each case connected to one of the word lines. In order to select a memory cell, in the case of a DRAM (Dynamic Random Access Memory), for example, selection transistors of memory cells are turned on by an activated word line, as a result of which a data signal of a corresponding selected memory cell can subsequently be read out or written. To that end, the selected memory cell is connected via the selection transistor to one of the bit lines, via which the corresponding data signal is read out or written in.
For a memory cell access, usually a plurality of memory cells are read from or written to within an access cycle. By way of example, a number or all of the memory cells along an activated word line are read from or written to. Such a memory cell access is generally referred to as a so-called burst and the number of selected memory cells or the number of read-out or write steps to be performed within an access cycle is referred to as the burst length. At the beginning of the access, a start address is applied to the memory and the access to the memory cells that are to be addressed within a burst is controlled internally without a new address in each case being applied to the memory.
The burst length is usually programmed in a so-called mode register. In an access cycle, a respective decoder which is assigned to a memory cell array is addressed for the selection of a word line and a number of bit lines (depending on the burst length). The decoder carries out the actions of activation, reading or writing and precharging, or selects the relevant word line and relevant bit lines therefor. After such an access, for a new memory cell access, a new word line is addressed and the actions described are in each case carried out anew. As a result, a burst length is generally limited to the length of the selected word line, the so-called page length of the memory.
It is accordingly an object of the invention to provide an integrated memory which overcomes the above-mentioned disadvantages of the heretofore-known memory devices of this general type and which allows to set a comparatively large variable burst length of the memory. Furthermore, it is an object of the invention to provide a method for operating an integrated memory that makes it possible to have a comparatively large variable burst length of the memory, in the case of a memory cell access.
With the foregoing and other objects in view there is provided, in accordance with the invention, an integrated memory, including:
a plurality of memory cell arrays each having memory cells, word lines for selecting the memory cells, and bit lines for reading data signals from the memory cells or writing data signals to the memory cells;
decoders assigned to respective ones of the memory cell arrays for selecting the bit lines and the word lines;
a terminal for receiving a read command or a write command, the read command and the write command having a respective state;
a control circuit for controlling a memory cell access, the control circuit being connected to the decoders and to the terminal for receiving a read command or a write command;
the control circuit generating, in dependence of the respective state of the read command or the write command, first control signals for driving one of the decoders assigned to one of the memory cell arrays and second control signals for driving a further one of the decoders assigned to a further one of the memory cell arrays within an access cycle; and
the control circuit being configured such that a generation of the first and second control signals by the control circuit is terminated by the read command or the write command.
In other words, the object of the invention is achieved by an integrated memory in which the memory cell arrays are in each case assigned a decoder for the selection of bit lines and word lines, a control circuit, which is connected to the respective decoders of the memory cell arrays and to a terminal for a read command or a write command, in which, for a memory cell access, the control circuit, depending on a state of the read command or write command can generate first control signals for driving the decoder of one of the memory cell arrays and second control signals for driving the decoder of a further memory cell array within an access cycle, and in which the generation of the control signals by the control circuit is terminated by the read command or write command.
With the objects of the invention in view there is also provided, a method for operating an integrated memory, the method includes the steps of:
providing an integrated memory having a plurality of memory cell arrays each having word lines for selecting memory cells and bit lines for reading or writing data signals of the memory cells;
generating a write command having an active state or a read command having an active state in order to trigger an access cycle for a memory cell access;
driving respective decoders of the memory cell arrays within the access cycle for the memory cell access; and
successively reading data from each of the memory cell arrays or successively writing data to each of the memory cell arrays for as long as the command remains in the active state.
In other words, the object of the invention is achieved by a method for operating an integrated memory having a plurality of memory cell arrays, which each have word lines for the selection of memory cells and bit lines for reading out or writing data signals of the memory cells, in which a write command or read command with an active state is generated in order to trigger an access cycle for a memory cell access, in which, for a memory cell access, within the access cycle respective decoders of the memory cell arrays are driven and data of each of the memory cell arrays are successively read out or written in for as long as the read command or write command remains in the active state.
The invention makes it possible to set comparatively large burst lengths of the memory for a memory cell access. To that end, provision is made of a plurality of memory cell arrays, for example in the form of memory banks, which are driven in so-called multi-memory-bank operation. This makes it possible to carry out a burst over all the memory cell arrays of the integrated memory. With this functionality, it is possible, in principle, to carry out bursts of virtually arbitrary length. The respective read command or write command is used to determine the burst length. This is achieved in that the data of each of the memory cell arrays are successively read out or written in for as long as the read command or write command remains in the active state. As soon as the read command or write command undergoes transition into an inactive state, the respective burst is ended. Accordingly, the control circuit is connected to the terminal for the read command or the write command, so that it can be indicated to the control circuit when the read or write access is ended. In this case, the generation of the control signals for driving the respective decoders is ended.
According to one embodiment of the integrated memory, the control circuit contains a counter circuit, which can be driven by the write command or read command. By way of example, the counter circuit generates the second control signals sequentially after the first control signals. Thus, firstly a burst is carried out at one of the memory cell arrays before the burst is continued at a further memory cell array.
As an alternative to this, it is possible for the counter circuit to generate the first control signals and second control signals alternately. The memory cell arrays are thus accessed in so-called interleave operation. Accordingly, data from a first memory cell array and data from a second memory cell array are read out or written in in an alternating order, whereas in the case of the sequential order described above, firstly data from a first memory cell array and then data from a second memory cell array are read out or written in.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a integrated memory having a plurality of memory cell arrays and a method for operating the integrated memory, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.